This invention relates to an access request control apparatus in a data processing system and more specifically to the determination of priority between a plurality of access requests, and more particularly to a processing system of memory access requests from central processing units (CPU's) and channel processing units (CHP's).
FIG. 1 is an example of a structure of a data processing system to which the present invention is applied. In this figure, blocks 1 and 2 are two central processing units CPU.sub.0 and CPU.sub.1, respectively; blocks 3 and 4 are four channel processing units CHP.sub.0 to CHP.sub.3 ; block 5 is a memory control unit MCU for the pipeline system 17; and block 6 is a memory unit MSU. Block 7 is a buffer memory BS, for example, of a set associative system. Block 8 is a directory to be used for controlling the buffer memory BS 7. Block 9 is a priority determination circuit. Block 10 is a pipeline 17 consisting of multistage registers.
The MCU 5 accepts the access requests for access to the MSU 6 at any time from any of the CPU.sub.0 1, CPU.sub.1 2, CHP.sub.0 3, . . . , CHP.sub.3 4 and executes memory control based on the buffer system, using the directory 8 and the buffer memory BS 7. Memory control by the buffer system means that the directory 8 is searched whether the data block to which an access request has been issued is or is not in the BS 7. When the data block exists in the BS 7, an access is carried out to the BS 7, but if it does not exist in the BS 7, access is made to the MSU and the pertinent block is loaded into the BS 7. When a plurality of access requests are accepted simultaneously by a conventional system, the priority determination circuit selects one access request according to a constant priority determination formula and the selected access request is executed.
The priority determination system for access requests can be summarized as follows. Between CHP and CPU, the CHP is given a higher priority. Between CPU and CPU, priority is determined in accordance with the priority determination formula for each unit. An access request from the loop-back (described later) should have the highest priority (see for example, Japanese laidopen Pat. No. 164338/1982 published 10/8/1982).
The operation of the priority determination system will now be outlined. The MCU 5 determines the priority when it accepts the access requests from a plurality of CHP's and CPU's and executes pipeline processing for the accepted access requests. First, priority is determined between CHP's in order to select one access request. Second, priority is determined between the selected CHP access request, access requests from a plurality of CPU's and a loop-back access request which is passing through the pipeline 17 again. As a result, one access request is selected. Thereafter, the selected access requests are sequentially input to the pipeline 17 in order to be executed.
A CHP access request, once it has been selected by the first priority determination process, may have its priority nullified in one of four ways:
(1) If the CHP access request and an access request sent from the loop-back are both present during the second priority determination step, the loop-back access request must obtain the highest priority in order to use the pipeline 17 again. Accordingly, since the priority of the loop-back access request is set higher than the CHP access request, the CHP access request cannot obtain the highest priority and the priority acquired in the first priority determination step is nullified.
(2) When the bank of buffer memory BS 7 to be used by the CHP access request is in use by another access request being processed by the MCU 5 or the signal for inhibiting access by the requesting CHP unit is being generated, the priority determined by the first priority determination step is nullified.
(3) When the data to be accessed by the access request is not in the buffer memory BS 7 (BUFFER NOT FOUND), after the CHP access which has obtained priority in the second priority determination is input to the pipeline, the main memory must be accessed. If it is detected that the main memory access port is in the busy state, the access request is nullified.
(4) When the set address of the buffer memory BS 7 used by the preceding access request is found to be the same as that of the CHP access request, set conflict occurs and the CHP access request is inhibited, nullified and started again from the first priority determination step.
A CHP access request which has been nullified and started again from the first priority determination step competes with other CHP access requests. Therefore, a CHP access request which should have been processed earlier may sometimes be delayed by later CHP access requests. Here arises a problem in that the access time of the CHP access request which should have been processed earlier is further increased due to a series of CHP access requests received later by the MCU 5.
On the other hand, a CHP access request which has had its priority nullified during the second priority determination step is not started again from the first priority determination step but is held until priority can be obtained in the second priority determination step. In this case, hardware for holding access requests which have had their priority nullified is necessary and a control circuit is necessary for determining whether a new CHP access request or a waiting CHP access request should take part in the second priority determination step.
The first and second priority determination logic in the existing system described above is not sufficiently flexible. The access requests which the MCU 5 processes include those which require repeated operations, like a block access request, and those from the loop-back having a comparatively low priority, like a prefetch request, or a comparatively high priority like an error processing request. In the existing priority determination system described above, the differences are all ignored and therefore processing is sometimes performed inefficiently.